Specifications

7-20

7.6 Register Bit Descriptions

7.6.1 ADC Control Register 1

Figure 7–7. ADC Control Register 1 (ADCTRL1) — Address 70A0h

15 14 13 12 11 10 9 8

Reserved RESET SOFT FREE ACQ_PS3 ACQ_PS2 ACQ_PS1 ACQ_PS0

RS-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

76543210

CPS

CONT_RUN INT_PRI SEQ_CASC CAL_ENA BRG_ENA HI/LO

STEST_

ENA

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Bit 15 Reserved

Bit 14 RESET. ADC module software reset

This bit causes a master reset on the entire ADC module. All register bits and

sequencer state machines are reset to the initial state as occurs when the de-

vice reset pin is pulled low (or after a power-on reset).

0 No effect

1 Resets entire ADC module (bit is then set back to 0 by ADC

logic)

Bits 13, 12 SOFT and FREE. Soft and Free bits

These bits determine what occurs when an emulation-suspend occurs (due

to the debugger hitting a breakpoint, for example). In free-run mode, the pe-

ripheral can continue with whatever it is doing. In stop mode, the peripheral can

either stop immediately or stop when the current operation (i.e., the current

conversion) is complete.

Soft Free

0 0 Immediate stop on suspend

1 0 Complete current conversion before stopping

X 1 Free run, continue operation regardless of suspend