Specifications

Calibration
7-18
7.4 Calibration
In the calibration mode, the sequencers are not operational and the ADCINn
pins are not connected to the A/D converter. The signal that gets connected
to the A/D converter input is determined by BRG_ENA (Bridge Enable) and
HI/LO (V
REFHI
/V
REFLO
selection) bits. These two signals connect either
V
REFLO
or V
REFHI
or their midpoint to the A/D converter input and a single con-
version is then done. The calibration mode can calculate the zero, midpoint or
full-scale offset errors of the ADC. The 2’s complement of the offset error
should then be loaded in the CALIBRATION register. From that point on, the
ADC hardware automatically adds the offset error to the converted value.
To summarize, the CALIBRATION register stores the end result of calibration
in the calibration mode. In the normal mode of the ADC, the value in the CAL-
IBRATION register is automatically added to the output of the ADC before the
result is stored in the RESULTn register.
In order to obtain the best results for midpoint offset calcualtions, both
|(V
REFHI
– V
REFLO
)/2| and |(V
REFLO
– V
REFHI
)/2| must be used as the refer-
ence voltage and the calibration done. The two results should then be aver-
aged.