Specifications

ADC Clock Prescaler
7-16
7.3 ADC Clock Prescaler
The S/H block in the ’240x ADC can be tailored to accomodate the variation
in source impedances. This is achieved by the ACQ_PS3–ACQ_PS0 bits and
the CPS bit in the ADCTR1 register. The analog-to-digital conversion process
can be divided into two time segments, as shown in Figure 7–5.
Figure 7–5. ADC Conversion Time
• • • • • •
S/H Window
(2 * PS)
Conversion
(11 * A
CLK
)
1 Complete ADC Conversion
PS = a prescaled CPU clock
PS will be the same as the CPU clock if the prescaler = 1 (i.e.,
ACQ_PS3–ACQ_PS0 bits are all zero) and if CPS = 0. For any other value of
the prescaler, the magnitude of PS will be magnified (effectively increasing the
S/H window time) as described by the “Acquisition Time Window” column in
the bit description for ACQ_PS3–ACQ_PS0. If the CPS bit is made 1, the S/H
window is doubled. This doubling of the S/H window is in addition to the
“stretching” provided by the prescaler. Figure 7–6 shows the role played by the
various prescaler bits in the ADC module. Note that PS and A
CLK
will be equal
to CPU clock if CPS = 0.