Specifications

ADC Overview
7-12
7.2.4 Input Trigger Description
Each sequencer has a set of trigger inputs that can be enabled/disabled. The
valid input triggers for SEQ1, SEQ2, and cascaded SEQ is as follows:
SEQ1 (sequencer 1) SEQ2 (sequencer 2) Cascaded SEQ
Software trigger (software SOC) Software trigger (software SOC) Software trigger (software SOC)
Event manager A (EVA SOC) Event manager B (EVB SOC) Event manager A (EVA SOC)
External SOC pin (ADC_SOC) Event manager B (EVB SOC)
External SOC pin (ADC_SOC)
Note that:
- A SOC trigger can initiate an autoconversion sequence whenever a se-
quencer is in “idle” state. An idle state is either CONV00 prior to receiving
a trigger, or any state which the sequencer lands on at the completion of
a conversion sequence, i.e., when SEQ_CNTR_n has reached a count of
zero.
- If a SOC trigger occurs while a current conversion sequence is underway,
it sets the SOC_SEQn bit (which would have been cleared on the com-
mencement of a previous conversion sequence) in the ADCTRL2 register.
If yet another SOC trigger occurs, it is lost (i.e., when the SOC_SEQn bit
is already set (SOC pending), subsequent triggers will be ignored).
- Once triggered, the sequencer cannot be stopped/halted in mid se-
quence. The program must either wait until an End of Sequence (EOS) or
initiate a sequencer reset, which brings the sequencer immediately back
to the idle start state (CONV00 for SEQ1 and cascaded cases; CONV08
for SEQ2).
- When SEQ1/2 are used in cascaded mode, triggers going to SEQ2 are ig-
nored, while SEQ1 triggers are active. Cascaded mode can be viewed as
SEQ1 with 16 states instead of 8.
7.2.5 Interrupt Operation During Sequenced Conversions
The sequencer can generate interrupts under two operating modes. These
modes are determined by the Interrupt-Mode-Enable Control bits in
ADCTRL2.
A variation of Example 7–2 can be used to show how interrupt mode 1 and
mode 2 are useful under different operating conditions.