Specifications

ADC Overview
7-10
Figure 7–3. Example of Event Manager Triggers to Start the Sequencer
25 µs
50 µs
EV1 Timer 1
Counter
EV1
PWM
I
1
,I
2
,I
3
V
1
,V
2
,V
3
I
1
,I
2
,I
3
V
1
,V
2
,V
3
Here MAX_CONV1 is set to 2 and the ADC Input Channel Select Sequencing
Control Registers (CHSELSEQn) are set to:
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A3h V
1
I
3
I
2
I
1
CHSELSEQ1
70A4h x x V
3
V
2
CHSELSEQ2
70A5h x x x x CHSELSEQ3
70A6h x x x x CHSELSEQ4
Once reset and initialized, SEQ1 waits for a trigger. With the first trigger, three
conversions with channel-select values of: CONV00 (I
1
), CONV01 (I
2
), and
CONV02 (I
3
) are performed. SEQ1 then waits at current state for another trig-
ger. Twenty-five microseconds later when the second trigger arrives, another
three conversions occur, with channel-select values of CONV03 (V
1
),
CONV04 (V
2
), and CONV05 (V
3
).
The value of MAX_CONV1 is automatically loaded into SEQ_CNTR_n for both
trigger cases. If a different number of conversions are required at the second
trigger point, the user must (at some appropriate time before the second trig-
ger) change the value of MAX_CONV1 through software, otherwise, the cur-
rent (originally loaded) value will be reused. This can be done by an ISR that
changes the value of MAX_CONV1 at the appropriate time. The interrupt op-
eration modes are described in section 7.2.5, “Interrupt Operation During Se-
quenced Conversions”.