Specifications

ADC Overview
7-9 Analog-to-Digital Converter (ADC)
- If CONT_RUN is not set, the sequencer stays in the last state (CONV06,
in this example) and SEQ_CNTR_n continues to hold a value of zero.
Since the interrupt flag is set every time SEQ_CNTR_n reaches zero, the user
can (if needed) manually reset the sequencer (using the RST_SEQn bit in the
ADCTRL2 register) in the Interrupt Service Routine (ISR), so that
SEQ_CNTR_n gets reloaded with the original value in MAX_CONV1 and
SEQ1 state is set to CONV00. This feature is useful in the “Start/Stop” opera-
tion of the sequencer. Example 7–1 also applies to SEQ2 and the cascaded
16-state sequencer (SEQ) with differences outlined in Table 7–2.
7.2.3 Sequencer “Start/Stop” Operation With Multiple “Time-Sequenced Triggers”
In addition to the mode described above, any sequencer (SEQ1, SEQ2, or
SEQ) can be operated in a “stop/start” mode which is synchronized to multiple
start-of-conversion (SOC) triggers, separated in time. This mode is identical
to Example 7–1, but the sequencer is allowed to be retriggered without being
reset to the initial state CONV00, once it has finished its first sequence (i.e.,
the sequencer is not reset in the interrupt service routine). Therefore, when
one conversion sequence ends, the sequencer stays in the current conversion
state. The Continuous Run bit (CONT_RUN) in the ADCTRL1 register must
be set to 0 (i.e., disabled) for this mode.
Example 7–2. Sequencer “Start/Stop” Operation
Requirement: To start three autoconversions (e.g., I
1
,I
2
,I
3
) off trigger 1 (under-
flow) and three autoconversions (e.g., V
1
,V
2
,V
3
) off trigger 2 (period). Trig-
gers 1 and 2 are separated in time by, say, 25 µs and are provided by Event
Manager A (EVA). See Figure 7–3. Only SEQ1 is used in this case.
Note: Triggers 1 and 2 may be a SOC signal from EVA, external pin, or soft-
ware. The same trigger source may occur twice to satisfy the dual-trigger re-
quirement of this example.