Specifications

ADC Overview
7-8
stored in one of the eight result registers (RESULT0 – RESULT7 for SEQ1 and
RESULT8 – RESULT15 for SEQ2). These registers are filled from the lowest
address to the highest address.
The number of conversions in a sequence is controlled by MAX_CONVn (a
3-bit or 4-bit field in the MAX_CONV register), which is automatically loaded
into the Sequencing Counter Status bits (SEQ_CNTR3 – 0) in the Autose-
quence Status Register (AUTO_SEQ_SR) at the start of an autosequenced
conversion session. The MAX_CONVn field can have a value ranging from
0 to 7. SEQ_CNTRn bits count down from their loaded value as the sequencer
starts from state CONV00 and continues sequentially (CONV01, CONV02,
and so on) until SEQ_CNTRn has reached zero. The number of conversions
completed during an autosequencing session is equal to (MAX_CONVn + 1).
Example 7–1. Conversion in Dual-Sequencer Mode Using SEQ1
Suppose seven conversions are desired from SEQ1 (i.e., Channels 2, 3, 2, 3,
6, 7, and 12 need to be converted as part of the autosequenced session), then
MAX_CONV1 should be set to 6 and the CHSELSEQn registers should be set
to the values shown in the table below:
Bits 15–12 Bits 11–8 Bits 7–4 Bits 3–0
70A3h 3
2 3 2 CHSELSEQ1
70A4h x 12 7 6 CHSELSEQ2
70A5h x x x x CHSELSEQ3
70A6h x x x x CHSELSEQ4
Note: Values are in decimal, and x = don’t care
Conversion begins once the start-of-conversion (SOC) trigger is received by
the sequencer. The SOC trigger also loads the SEQ_CNTR_n bits. Those
channels that are specified in the CHSELSEQn registers are taken up for con-
version, in the predetermined sequence. The SEQ_CNTR_n bits are decrem-
ented by one automatically after every conversion. Once SEQ_CNTR_n
reaches zero, two things can happen depending on the status of the Continu-
ous Run bit (CONT_RUN) in the ADCTRL1 register.
- If CONT_RUN is set, the conversion sequence starts all over again auto-
matically (i.e., SEQ_CNTR_n gets reloaded with the original value in
MAX_CONV1 and SEQ1 state is set to CONV00). In this case, the user
must ensure that the result registers are read before the next conversion
sequence begins. The arbitration logic designed into the ADC ensures
that the result registers are not corrupted should a contention arise (ADC
module trying to write into the result registers while the user tries to read
from them at the same time).