Specifications

ADC Overview
7-6
Figure 7–2. Block Diagram of Autosequenced ADC With Dual Sequencers
ADCIN0
ADCIN1
ADCIN2
ADCIN15
MAX_CONV1
Ch Sel (state 0)
Ch Sel (state 1)
Ch Sel (state 3)
Ch Sel (state 2)
Ch Sel (state 7)
State
pointer
10-bit, 500-ns
S/H + A/D
converter
SOC EOC
10
Analog MUX
Result MUX
Result
Select
10
RESULT0
RESULT1
RESULT7
SEQ1
Software
EVA
External pin (ADCSOC)
Select
MUX
Note: Possible values:
Channel Select = 0 to 15
MAX_CONV1 = 0 to 7
Sequencer
arbiter
SOC1 EOC1
44
4
MUX
Ch Sel (state 15)
Ch Sel (state 8)
Ch Sel (state 9)
Ch Sel (state 11)
Ch Sel (state 10)
EVB
MAX_CONV2
SOC2
EOC2
4
State
pointer
Software
SEQ2
Start of
sequence
trigger trigger
sequence
Start of
Result
Select
RESULT15
10
Result MUX
RESULT9
RESULT8
10
10
MAX_CONV2 = 8 to 15