Specifications

Features
7-2
7.1 Features
- 10-bit ADC core with built-in Sample and Hold (S/H)
- Fast conversion time (S/H + Conversion) of 500 ns
- Sixteen multiplexed analog inputs (ADCIN0 – ADCIN15). Eight in ’2402
- Autosequencing capability – up to 16 “autoconversions” in a single ses-
sion. Each conversion session can be programmed to select any one of
the 16 input channels.
- Two independent 8-state sequencers (SEQ1 and SEQ2) that can be oper-
ated individually in “dual-sequencer mode” or cascaded into one large
16-state sequencer (SEQ) in “cascaded mode”
- Four Sequencing Control Registers (CHSELSEQn) that determine the se-
quence of analog channels that are taken up for conversion in a given se-
quencing mode
- Sixteen (individually addressable) result registers to store the converted
values (RESULT0 – RESULT15)
- Multiple trigger sources for start-of-conversion (SOC) sequence
J Software: Software immediate start (using SOC_SEQn bit)
J EVA: Event manager A (multiple event sources within EVA)
J EVB: Event manager B (multiple event sources within EVB)
J External: ADCSOC pin
- Flexible interrupt control allows interrupt request on every End of Se-
quence (EOS) or every other EOS
- Sequencer can operate in “start/stop” mode, allowing multiple “time-
sequenced triggers” to synchronize conversions
- EVA and EVB can independently trigger SEQ1 and SEQ2, respectively.
(This is applicable for dual-sequencer mode only.)
- Sample-and-hold acquisition time window has separate prescale control
- Built-in calibration mode
- Built-in “self-test” mode