Specifications

Event Manager (EV) Interrupts
6-96
Bit 0 PDPINTB ENABLE. This is enabled (set to 1) following reset.
0 Disable
1 Enable
EVB Interrupt Mask Register B (EVBIMRB)
Figure 6–46. EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh
15–4 3210
Reserved
T4OFINT
ENABLE
T4UFINT
ENABLE
T4CINT
ENABLE
T4PINT
ENABLE
R-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–4 Reserved. Reads return zero; writes have no effect.
Bit 3 T4OFINT ENABLE
0 Disable
1 Enable
Bit 2 T4UFINT ENABLE
0 Disable
1 Enable
Bit 1 T4CINT ENABLE
0 Disable
1 Enable
Bit 0 T4PINT ENABLE
0 Disable
1 Enable
EVB Interrupt Mask Register C (EVBIMRC)
Figure 6–47. EVB Interrupt Mask Register C (EVBIMRC) — Address 752Eh
15–3 2 1 0
Reserved
CAP6INT
ENABLE
CAP5INT
ENABLE
CAP4INT
ENABLE
R-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset