Specifications

Event Manager (EV) Interrupts
6-95 Event Manager (EV)
EVB Interrupt Mask Register A (EVBIMRA)
Figure 6–45. EVB Interrupt Mask Register A (EVBIMRA) — Address 752Ch
15–11 10 9 8
Reserved
T3OFINT
ENABLE
T3UFINT
ENABLE
T3CINT
ENABLE
R-0 RW-0 RW-0 RW-0
7 6–4 3210
T3PINT
ENABLE
Reserved
CMP6INT
ENABLE
CMP5INT
ENABLE
CMP4INT
ENABLE
PDPINTB
ENABLE
RW-0 R-0 RW-0 RW-0 RW-0 RW-1
Note: R = Read access, W = Write access, -n = value after reset
Bits 15–11 Reserved. Reads return zero; writes have no effect.
Bit 10 T3OFINT ENABLE
0 Disable
1 Enable
Bit 9 T3UFINT ENABLE
0 Disable
1 Enable
Bit 8 T3CINT ENABLE
0 Disable
1 Enable
Bit 7 T3PINT ENABLE
0 Disable
1 Enable
Bits 6–4 Reserved. Reads return zero; writes have no effect.
Bit 3 CMP6INT ENABLE
0 Disable
1 Enable
Bit 2 CMP5INT ENABLE
0 Disable
1 Enable
Bit 1 CMP4INT ENABLE
0 Disable
1 Enable