Specifications

Event Manager (EV) Interrupts
6-90
Bit 0 PDPINTA ENABLE. This is enabled (set to 1) following reset.
0 Disable
1 Enable
EVA Interrupt Mask Register B (EVAIMRB)
Figure 6–40. EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh
15–4 3210
Reserved
T2OFINT
ENABLE
T2UFINT
ENABLE
T2CINT
ENABLE
T2PINT
ENABLE
R-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–4 Reserved. Reads return zero; writes have no effect.
Bit 3 T2OFINT ENABLE
0 Disable
1 Enable
Bit 2 T2UFINT ENABLE
0 Disable
1 Enable
Bit 1 T2CINT ENABLE
0 Disable
1 Enable
Bit 0 T2PINT ENABLE
0 Disable
1 Enable
EVA Interrupt Mask Register C (EVAIMRC)
Figure 6–41. EVA Interrupt Mask Register C (EVAIMRC) — Address 742Eh
15–3 2 1 0
Reserved
CAP3INT
ENABLE
CAP2INT
ENABLE
CAP1INT
ENABLE
R-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset