Specifications

Event Manager (EV) Interrupts
6-85 Event Manager (EV)
Interrupt Vector
The peripheral interrupt vector corresponding to the interrupt flag that has the
highest priority among the flags that are set and enabled is loaded into the
PIVR when an interrupt request is acknowledged (this is all done in the periph-
eral interrupt controller, external to the event manager peripheral).
Failure to Clear the Interrupt Flag Bit
The interrupt flag bit in the peripheral register must be cleared by
software writing a 1 to the bit in the ISR. Failure to clear this bit will
prevent future interrupt requests by that source.
6.10.2 EV Interrupt Flag Registers
Addresses of the EVA interrupt registers and the EVB interrupt registers are
shown in Table 6–9 and Table 6–10, respectively, on page 6-13. The registers
are all treated as 16-bit memory mapped registers. The unused bits all return
zero when read by software. Writing to unused bits has no effect. Since
EVxIFRx are readable registers, occurrence of an interrupt event can be moni-
tored by software polling the appropriate bit in EVxIFRx when the interrupt is
masked.
EVA Interrupt Flag Register A (EVAIFRA)
Figure 6–36. EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh
15–11 10 9 8
Reserved
T1OFINT
FLAG
T1UFINT
FLAG
T1CINT
FLAG
R-0 RW-0 RW-0 RW-0
7 6–4 3210
T1PINT
FLAG
Reserved
CMP3INT
FLAG
CMP2INT
FLAG
CMP1INT
FLAG
PDPINTA
FLAG
RW-0 R-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset