Specifications

Figures
xx
8–19 Transmit Data Buffer Register (SCITXBUF) — Address 7059h 8-30. . . . . . . . . . . . . . . . . . . . .
8–20 SCI Priority Control Register (SCIPRI) — Address 705Fh 8-31. . . . . . . . . . . . . . . . . . . . . . . . .
9–1 SPI Module Block Diagram 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–2 SPI Master/Slave Connection 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–3 SPICLK Signal Options 9-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–4 SPI: SPICLK-CLKOUT Characteristic when (BRR + 1) is Odd, BRR > 3, and
CLOCK POLARITY = 1 9-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–5 Five Bits per Character 9-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–6 SPI Control Registers 9-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–7 SPI Configuration Control Register (SPICCR) — Address 7040h 9-18. . . . . . . . . . . . . . . . . . .
9–8 SPI Operation Control Register (SPICTL) — Address 7041h 9-20. . . . . . . . . . . . . . . . . . . . . . .
9–9 SPI Status Register (SPISTS) — Address 7042h 9-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–10 SPI Baud Rate Register (SPIBRR) — Address 7044h 9-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–11 SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h 9-24. . . . . . . . . . . . . . . . . . . .
9–12 SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h 9-25. . . . . . . . . . . . . . . . .
9–13 SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h 9-26. . . . . . . . . . . . . . . .
9–14 SPI Serial Data Register (SPIDAT) — Address 7049h 9-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–15 SPI Priority Control Register (SPIPRI) — Address 704Fh 9-28. . . . . . . . . . . . . . . . . . . . . . . . . .
9–16 CLOCK_POLARITY = 0, CLOCK_PHASE = 0 (All data transitions are during
the rising edge. Inactive level is low.) 9-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–17 CLOCK_POLARITY = 0, CLOCK_PHASE = 1 (Add data transitions are during
the rising edge, but delayed by half clock cycle. Inactive level is low.) 9-30. . . . . . . . . . . . . . .
9–18 CLOCK_POLARITY = 1, CLOCK_PHASE = 0 (All data transitions are during
the falling edge. Inactive level is high.) 9-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–19 CLOCK_POLARITY = 1, CLOCK_PHASE = 1 (Add data transitions are during
the falling edge, but delayed by half clock cycle. Inactive level is high.) 9-32. . . . . . . . . . . . . .
9–20 SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits
of transmission.) 9-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–21 SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits
of transmission.) 9-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–1 CAN Data Frame 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–2 TMS320x240x CAN Module Block Diagram 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–3 TMS320x240x CAN Module Memory Space 10-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–4 CAN Data Frame 10-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–5 Message Identifier for High Word Mailboxes 0–5 (MSGIDnH) 10-10. . . . . . . . . . . . . . . . . . . . .
10–6 Message Identifier for Low Word Mailboxes 0–5 (MSGIDnL) 10-11. . . . . . . . . . . . . . . . . . . . . .
10–7 Message Control Field (MSGCTRLn) 10-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–8 Remote Frame Requests 10-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–9 Local Acceptance Mask Register n (0, 1) High Word (LAMn_H) 10-17. . . . . . . . . . . . . . . . . . .
10–10 Local Acceptance Mask Register n (0, 1) Low Word (LAMn_L) 10-17. . . . . . . . . . . . . . . . . . . .
10–11 Mailbox Direction/Enable Register (MDER) — Address 7100h 10-18. . . . . . . . . . . . . . . . . . . .
10–12 Transmission Control Register (TCR) — Address 7101h 10-19. . . . . . . . . . . . . . . . . . . . . . . . .
10–13 Receive Control Register (RCR) — Address 7102h 10-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–14 Master Control Register (MCR) — Address 7103h 10-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10–15 Bit Configuration Register 2 (BCR2) — Address 7104h 10-25. . . . . . . . . . . . . . . . . . . . . . . . . . .