Specifications

Capture Units
6-76
CAP4FBOT, CAP5FBOT, and CAP6FBOT (in case of EVB). The top-level reg-
ister of any of the FIFO stacks is a read-only register that always contains the
oldest counter value captured by the corresponding capture unit. Therefore,
a read access to the FIFO stack of a capture unit always returns the oldest
counter value stored in the stack. When the oldest counter value in the top reg-
ister of the FIFO stack is read, the newer counter value in the bottom register
of the stack, if any, is pushed into the top register.
If desired, the bottom register of the FIFO stack can be read. Reading the bot-
tom register of the FIFO stack causes the FIFO status bits to change to 01 (has
one entry), if they were previously 10 or 11. If the FIFO status bits were pre-
viously 01 when the bottom FIFO register is read, they will change to 00
(empty).
First Capture
The counter value of the selected GP timer (captured by a capture unit when
a specified transition happens on its input pin) is written into the top register
of the FIFO stack, if the stack is empty. At the same time, the corresponding
status bits are set to 01. The status bits are reset to 00 if a read access is made
to the FIFO stack before another capture is made.
Second Capture
If another capture occurs before the previously captured counter value is read,
the newly captured counter value goes to the bottom register. In the mean time,
the corresponding status bits are set to (10). When the FIFO stack is read be-
fore another capture happens, the older counter value in the top register is
read out, the newer counter value in the bottom register is pushed up into the
top register, and the corresponding status bits are set to 01.
The appropriate capture interrupt flag is set by the second capture. A peripher-
al interrupt request is generated if the interrupt is not masked.
Third Capture
If a capture happens when there are already two counter values captured in
the FIFO stack, the oldest counter value in the top register of the stack is
pushed out and lost, the counter value in the bottom register of the stack is
pushed up into the top register, the newly captured counter value is written into
the bottom register, and the status bits are set to 11 to indicate one or more
older captured counter values have been lost.
The appropriate capture interrupt flag is also set by the third capture. A periph-
eral interrupt request is generated if the interrupt is not masked.