Specifications

Capture Units
6-74
Figure 6–31. Capture FIFO Status Register A (CAPFIFOA) — Address 7422h
15–14 13–12 11–10 9–8
Reserved CAP3FIFO CAP2FIFO CAP1FIFO
R-0 RW-0 RW-0 RW-0
7–0
Reserved
R-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–14 Reserved. Reads return zero; writes have no effect.
Bits 13–12 CAP3FIFO. CAP3FIFO Status.
00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been
lost.
Bits 11–10 CAP2FIFO. CAP2FIFO Status
00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been
lost.
Bits 9–8 CAP1FIFO. CAP1FIFO Status.
00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been
lost.
Bits 7–0 Reserved. Reads return zero; writes have no effect.
Capture FIFO Status Register B (CAPFIFOB)
CAPFIFOB contains the status bits for each of the three FIFO stacks of the
capture units. The bit description of CAPFIFOB is given in Figure 6–32. If a
write occurs to the CAPnFIFOB status bits at the same time as they are being
updated (because of a capture event), the write data takes precedence.