Specifications

Capture Units
6-72
Bits 3–2 CAP3EDGE. Edge detection control for Capture Unit 3.
00 No detection
01 Detect rising edge
10 Detect falling edge
11 Detect both edges
Bits 1–0 Reserved. Reads return zero; writes have no effect.
Capture Control Register B (CAPCONB)
Figure 6–30. Capture Control Register B (CAPCONB) — Address 7520h
15 14–13 12 11 10 9 8
CAPRES
CAPQEPN CAP6EN Reserved CAP6TSEL CAP45TSEL CAP6TOADC
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7–6 5–4 3–2 1–0
CAP4EDGE
CAP5EDGE CAP6EDGE Reserved
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 15 CAPRES. Capture reset. Always reads zero.
Note: This bit is not implemented as a register bit. Writing a 0 simply clears the
capture registers.
0 Clear all registers of capture units and QEP circuit to 0.
1 No action
Bits 14–13 CAPQEPN. Capture Units 4 and 5 and QEP circuit control.
00 Disable Capture Units 4 and 5 and QEP circuit. FIFO stacks retain
their contents.
01 Enable Capture Units 4 and 5, disable QEP circuit.
10 Reserved
11 Enable QEP circuit. Disable Capture Units 4 and 5; bits 4–7 and 9
are ignored.
Bit 12 CAP6EN. Capture Unit 6 control.
0 Disable Capture Unit 6; FIFO stack of Capture Unit 6 retains its
contents.
1 Enable Capture Unit 6