Specifications

Capture Units
6-70
Capture Unit Setup
For a capture unit to function properly, the following register setup must be per-
formed:
1) Initialize the CAPFIFOx and clear the appropriate status bits.
2) Set the selected GP timer in one of its operating modes.
3) Set the associated GP timer compare register or GP timer period register,
if necessary.
4) Set up CAPCONA or CAPCONB as appropriate.
6.8.3 Capture Unit Registers
The operation of the capture units is controlled by four 16-bit control registers,
CAPCONA/B and CAPFIFOA/B. TxCON (x = 1, 2, 3, or 4) registers are also
used to control the operation of the capture units since the time base for cap-
ture circuits can be provided by any of these timers. Additionally, CAPCONA/B
is also used to control the operation of the QEP circuit. Table 6–7 and
Table 6–8 on page 6-12 shows the addresses of these registers.
Capture Control Register A (CAPCONA)
Figure 6–29. Capture Control Register A (CAPCONA) — Address 7420h
15 14–13 12 11 10 9 8
CAPRES
CAPQEPN CAP3EN Reserved CAP3TSEL CAP12TSEL CAP3TOADC
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7–6 5–4 3–2 1–0
CAP1EDGE
CAP2EDGE CAP3EDGE Reserved
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 15 CAPRES. Capture reset. Always reads zero.
Note: This bit is not implemented as a register bit. Writing a 0 simply clears the
capture registers.
0 Clear all registers of capture units and QEP circuit to 0.
1 No action