Specifications

Capture Units
6-69 Event Manager (EV)
- Three 16-bit 2-level-deep FIFO stacks, one for each capture unit.
- Six Schmitt-triggered capture input pins, CAP1 through CAP6, one input
pin for each capture unit. (All inputs are synchronized with the device/CPU
clock: in order for a transition to be captured, the input must hold at its cur-
rent level to meet the two rising edges of the device clock. Input pins CAP1
and CAP2 (CAP4 and CAP5 in case of EVB) can also be used as QEP
inputs to QEP circuit)
- User-specified transition (rising edge, falling edge, or both edges) detec-
tion
- Six maskable interrupt flags, one for each capture unit
6.8.2 Operation of Capture Units
After a capture unit is enabled, a specified transition on the associated input
pin causes the counter value of the selected GP timer to be loaded into the cor-
responding FIFO stack. At the same time, if there are already one or more valid
capture values stored in the FIFO stack (CAPxFIFO bits not equal to zero) the
corresponding interrupt flag is set. If the flag is unmasked, a peripheral inter-
rupt request is generated. The corresponding status bits in CAPFIFOx are ad-
justed to reflect the new status of the FIFO stack each time a new counter value
is captured in a FIFO stack. The latency from the time a transition happens in
a capture input to the time the counter value of selected GP timer is locked is
two clock cycles.
All capture unit registers are cleared to 0 by a RESET condition.
Capture Unit Time Base Selection
For EVA, Capture Unit 3 has a separate time base selection bit from Capture
Units 1 and 2. This allows the two GP timers to be used at the same time, one
for Capture Units 1 and 2, and the other for Capture Unit 3. For EVB, Capture
Unit 6 has a separate time base selection bit.
Capture operation does not affect the operation of any GP timer or the
compare/PWM operations associated with any GP timer.