Specifications

Figures
xix Contents
6–34 Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB 6-79. . . . . . . . . . . . . . . . . . .
6–35 Quadrature Encoded Pulses and Decoded Timer Clock and Direction 6-80. . . . . . . . . . . . . . .
6–36 EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh 6-85. . . . . . . . . . . . . . . . . . . . . . .
6–37 EVA Interrupt Flag Register B (EVAIFRB) — Address 7430h 6-87. . . . . . . . . . . . . . . . . . . . . . .
6–38 EVA Interrupt Flag Register C (EVAIFRC) — Address 7431h 6-88. . . . . . . . . . . . . . . . . . . . . .
6–39 EVA Interrupt Mask Register A (EVAIMRA) — Address 742Ch 6-89. . . . . . . . . . . . . . . . . . . . .
6–40 EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh 6-90. . . . . . . . . . . . . . . . . . . . .
6–41 EVA Interrupt Mask Register C (EVAIMRC) — Address 742Eh 6-90. . . . . . . . . . . . . . . . . . . . .
6–42 EVB Interrupt Flag Register A (EVBIFRA) — Address 752Fh 6-91. . . . . . . . . . . . . . . . . . . . . .
6–43 EVB Interrupt Flag Register B (EVBIFRB) — Address 7530h 6-93. . . . . . . . . . . . . . . . . . . . . .
6–44 EVB Interrupt Flag Register C (EVBIFRC) — Address 7531h 6-94. . . . . . . . . . . . . . . . . . . . . .
6–45 EVB Interrupt Mask Register A (EVBIMRA) — Address 752Ch 6-95. . . . . . . . . . . . . . . . . . . . .
6–46 EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh 6-96. . . . . . . . . . . . . . . . . . . . .
6–47 EVB Interrupt Mask Register C (EVBIMRC) — Address 752Eh 6-96. . . . . . . . . . . . . . . . . . . . .
7–1 Block Diagram of Autosequenced ADC in Cascaded Mode 7-5. . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Block Diagram of Autosequenced ADC With Dual Sequencers 7-6. . . . . . . . . . . . . . . . . . . . . .
7–3 Example of Event Manager Triggers to Start the Sequencer 7-10. . . . . . . . . . . . . . . . . . . . . . .
7–4 Interrupt Operation During Sequenced Conversions 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 ADC Conversion Time 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 Clock Prescalers in ’240x ADC 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 ADC Control Register 1 (ADCTRL1) — Address 70A0h 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . .
7–8 ADC Control Register 2 (ADCTRL2) — Address 70A1h 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . .
7–9 Maximum Conversion Channels Register (MAX_CONV) — Address 70A2h 7-27. . . . . . . . .
7–10 Autosequence Status Register (AUTO_SEQ_SR) — Address 70A7h 7-29. . . . . . . . . . . . . . .
7–11 ADC Input Channel Select Sequencing Control Registers (CHSELSEQn) 7-31. . . . . . . . . . .
7–12 ADC Conversion Result Buffer Registers 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 SCI Block Diagram 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 Typical SCI Data Frame Formats 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–3 Idle-Line Multiprocessor Communication Format 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Double-Buffered WUT and TXSHF 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–5 Address-Bit Multiprocessor Communication Format 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–6 SCI Asynchronous Communications Format 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–7 SCI RX Signals in Communication Modes 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–8 SCI TX Signals in Communications Modes 8-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–9 SCI Control Registers 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–10 SCI Communication Control Register (SCICCR) — Address 7050h 8-20. . . . . . . . . . . . . . . . .
8–11 SCI Control Register 1 (SCICTL1) — Address 7051h 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–12 Baud-Select MSbyte Register (SCIHBAUD) — Address 7052h 8-25. . . . . . . . . . . . . . . . . . . . .
8–13 Baud-Select LSbyte Register (SCILBAUD) — Address 7053h 8-25. . . . . . . . . . . . . . . . . . . . . .
8–14 SCI Control Register 2 (SCICTL2) — Address 7054h 8-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–15 Receiver Status Register (SCIRXST) — Address 7055h 8-27. . . . . . . . . . . . . . . . . . . . . . . . . . .
8–16 Register SCIRXST Bit Associations — Address 7055h 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–17 Emulation Data Buffer Register (SCIRXEMU) — Address 7056h 8-30. . . . . . . . . . . . . . . . . . .
8–18 Receiver Data Buffer (SCIRXBUF) — Address 7057h 8-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .