Specifications

Capture Units
6-68
Figure 6–28. Capture Units Block Diagram (EVB)
T2CNT
GP timer 4
counter
T1CNT
GP timer 3
counter
MUX
Edge
detect
2-level
FIFO
stacks
Cap FIFO
status
ADC start
CAPCONB[15]
CAP4,5,6
CAPCONB[8]
2
16
16
8
6
6
3
CAPCONB[9,10]
CAPCONB[12–14]
RS
clear
CAPCONB[2–7]
Edge
select
Capture unit 6
cap. event
CAPFIFOB[13–15]
RS
EN
6.8.1 Capture Unit Features
Capture units have the following features:
- One 16-bit capture control register (CAPCONA for EVA, CAPCONB for
EVB), (RW)
- One 16-bit capture FIFO status register (CAPFIFOA for EVA, CAPFIFOB
for EVB)
- Selection of GP timer 1 or 2 (for EVA) and GP timer 3 or 4 (for EVB) as the
time base