Specifications

PWM Circuits Associated With Compare Units
6-49 Event Manager (EV)
Bit 5 EDBT1. Dead-band timer 1 enable (for pins PWM1 and PWM2 of Compare
Unit 1).
0 Disable
1 Enable
Bits 4–2 DBTPS2 to DBTPS0. Dead-band timer prescaler.
000 x/1
001 x/2
010 x/4
011 x/8
100 x/16
101 x/32
110 x/32
111 x/32
x = Device (CPU) clock frequency
Bits 1–0 Reserved. Reads return zero; writes have no effect.
Figure 6–19. Dead-Band Timer Control Register B (DBTCONB) — Address xx15h
15–12 11 10 9 8
Reserved DBT3 DBT2 DBT1 DBT0
R-0 RW-0 RW-0 RW-0 RW-0
765432 1–0
EDBT3
EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 Reserved
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–12 Reserved. Reads return zero; writes have no effect.
Bits 11–8 DBT3 (MSB)–DBT0 (LSB). Dead-band timer period. These bits define the pe-
riod value of the three 4-bit dead-band timers.
Bit 7 EDBT3. Dead-band timer 3 enable (for pins PWM11 and PWM12 of Compare
Unit 6).
0 Disable
1 Enable
Bit 6 EDBT2. Dead-band timer 2 enable (for pins PWM9 and PWM10 of Compare
Unit 5).
0 Disable
1 Enable