Specifications

PWM Circuits Associated With Compare Units
6-47 Event Manager (EV)
The PWM circuits are designed to minimize CPU overhead and user interven-
tion when generating pulse width modulated waveforms used in motor control
and motion control applications. PWM generation with compare units and as-
sociated PWM circuits are controlled by the following control registers:
T1CON, COMCONA, ACTRA, and DBTCONA (in case of EVA); and T3CON,
COMCONB, ACTRB, and DBTCONB (in case of EVB).
6.5.1 PWM Generation Capability of Event Manager
The PWM waveform generation capability of each event manager module
(A and B) is summarized as follows:
- Five independent PWM outputs, three of which are generated by the
compare units; the other two are generated by the GP timer compares,
plus three additional PWM outputs dependent on the three compare unit
PWM outputs
- Programmable dead-band for the PWM output pairs associated with the
compare units
- Minimum dead-band duration of one device clock cycle
- Minimum PWM pulsewidth and pulsewidth increment/decrement of one
clock cycle
- 16-bit maximum PWM resolution
- On-the-fly change of PWM carrier frequency (double buffered period reg-
isters)
- On-the-fly change of PWM pulsewidths (double buffered compare regis-
ters)
- Power Drive Protection Interrupt
- Programmable generation of asymmetric, symmetric, and space vector
PWM waveforms
- Minimum CPU overhead because of the auto-reloading of the compare
and period registers