Specifications

Compare Units
6-42
Bits 11–10 ACTRLD1, ACTRLD0. Action control register reload condition.
00 When T3CNT = 0 (on underflow)
01 When T3CNT = 0 or T3CNT = T3PR (on underflow or period
match)
10 Immediately
11 Reserved
Bit 9 FCOMPOE. Compare output enable. Active PDPINTx clears this bit to zero.
0 PWM output pins are in high-impedance state; that is, they are
disabled.
1 PWM output pins are not in high-impedance state; that is, they are
enabled.
Bits 8–0 Reserved. Read returns zero; writes have no effect.
Compare Action Control Registers (ACTRA and ACTRB)
The compare action control registers (ACTRA and ACTRB) control the action
that takes place on each of the six compare output pins (PWMx, where x = 1–6
for ACTRA, and x = 7–12 for ACTRB) on a compare event, if the compare op-
eration is enabled by COMCONx[15]. ACTRA and ACTRB are double-
buffered. The condition on which ACTRA and ACTRB is reloaded is defined
by bits in COMCONx. ACTRA and ACTRB also contain the SVRDIR, D2, D1,
and D0 bits needed for space vector PWM operation. The bit configuration of
ACTRA is described in Figure 6–15 and that of ACTRB is described in
Figure 6–16.
Figure 6–15. Compare Action Control Register A (ACTRA) — Address 7413h
15 14 13 12 11 10 9 8
SVRDIR
D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
CMP4ACT1
CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 15 SVRDIR. Space vector PWM rotation direction. Used only in space vector
PWM output generation.
0 Positive (CCW)
1 Negative (CW)