Specifications

Compare Units
6-40
Bit 15 CENABLE. Compare enable.
0 Disable compare operation. All shadowed registers (CMPRx,
ACTRA) become transparent.
1 Enable compare operation.
Bits14–13 CLD1, CLD0. Compare register CMPRx reload condition.
00 When T1CNT = 0 (that is, on underflow)
01 When T1CNT = 0 or T1CNT = T1PR (that is, on underflow or
period match)
10 Immediately
11 Reserved; result is unpredictable.
Bit 12 SVENABLE. Space vector PWM mode enable.
0 Disable space vector PWM mode.
1 Enable space vector PWM mode.
Bits 11–10 ACTRLD1, ACTRLD0. Action control register reload condition.
00 When T1CNT = 0 (on underflow)
01 When T1CNT = 0 or T1CNT = T1PR (on underflow or period
match)
10 Immediately
11 Reserved
Bit 9 FCOMPOE. Compare output enable. Active PDPINTx clears this bit to zero.
0 PWM output pins are in high-impedance state; that is, they are
disabled.
1 PWM output pins are not in high-impedance state; that is, they are
enabled.
Bits 8–0 Reserved. Read returns zero; writes have no effect.