Specifications

General-Purpose (GP) Timers
6-35 Event Manager (EV)
Bit 13 T3STAT. GP timer 3 Status. Read only.
0 Counting downward
1 Counting upward
Bits 12–11 Reserved. Reads return zero; writes have no effect.
Bits 10–9 T4TOADC. Start ADC with timer 4 event.
00 No event starts ADC.
01 Setting of underflow interrupt flag starts ADC.
10 Setting of period interrupt flag starts ADC.
11 Setting of compare interrupt flag starts ADC.
Bits 8–7 T3TOADC. Start ADC with timer 3 event.
00 No event starts ADC.
01 Setting of underflow interrupt flag starts ADC.
10 Setting of period interrupt flag starts ADC.
11 Setting of compare interrupt flag starts ADC.
Bit 6 TCOMPOE. Compare output enable. If PDPINTx
is active this bit is set to zero.
0 Disable all GP timer compare outputs (all compare outputs are put
in the high-impedance state).
1 Enable all GP timer compare outputs.
Bits 5–4 Reserved. Reads return zero; writes have no effect.
Bits 3–2 T4PIN. Polarity of GP timer 4 compare output.
00 Forced low
01 Active low
10 Active high
11 Forced high
Bits 1–0 T3PIN. Polarity of GP timer 3 compare output.
00 Forced low
01 Active low
10 Active high
11 Forced high
6.3.4 Generation of PWM Outputs Using the GP Timers
Each GP timer can independently be used to provide a PWM output channel.
Thus, up to two PWM outputs may be generated by the GP timers.