Specifications

General-Purpose (GP) Timers
6-34
Bits 8–7 T1TOADC. Start ADC with timer 1 event.
00 No event starts ADC.
01 Setting of underflow interrupt flag starts ADC.
10 Setting of period interrupt flag starts ADC.
11 Setting of compare interrupt flag starts ADC.
Bit 6 TCOMPOE. Compare output enable. If PDPINTx is active this bit is set to zero.
0 Disable all GP timer compare outputs (all compare outputs are put
in the high-impedance state).
1 Enable all GP timer compare outputs.
Bits 5–4 Reserved. Reads return zero; writes have no effect.
Bits 3–2 T2PIN. Polarity of GP timer 2 compare output.
00 Forced low
01 Active low
10 Active high
11 Forced high
Bits 1–0 T1PIN. Polarity of GP timer 1 compare output.
00 Forced low
01 Active low
10 Active high
11 Forced high
Overall GP Timer Control Register (GPTCONB)
Figure 6–11.GP Timer Control Register B (GPTCONB) — Address 7500h
15 14 13 12–11 10–9 8–7
Reserved T4STAT T3STAT Reserved T4TOADC T3TOADC
RW-0 R-1 R-1 RW-0 RW-0 RW-0
6 5–4 3–2 1–0
TCOMPOE
Reserved T4PIN T3PIN
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -n = value after reset
Bit 15 Reserved. Reads return zero; writes have no effect.
Bit 14 T4STAT. GP timer 4 Status. Read only.
0 Counting downward
1 Counting upward