Specifications

General-Purpose (GP) Timers
6-33 Event Manager (EV)
Bit 1 TECMPR. Timer compare enable.
0 Disable timer compare operation.
1 Enable timer compare operation.
Bit 0 SELT1PR. In case of EVA, this bit is SELT1PR. (Period register select.) This bit
is a reserved bit in T1CON.
SELT3PR. In case of EVB, this bit is SELT3PR. (Period register select.) This bit
is a reserved bit in T3CON.
0 Use own period register.
1 Use T1PR (in case of EVA) or T3PR (in case of EVB) as period
register ignoring own period register.
Overall GP Timer Control Register (GPTCONA)
Figure 6–10. GP Timer Control Register A (GPTCONA) — Address 7400h
15 14 13 12–11 10–9 8–7
Reserved T2STAT T1STAT Reserved T2TOADC T1TOADC
RW-0 R-1 R-1 RW-0 RW-0 RW-0
6 5–4 3–2 1–0
TCOMPOE
Reserved T2PIN T1PIN
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -n = value after reset
Bit 15 Reserved. Reads return zero; writes have no effect.
Bit 14 T2STAT. GP timer 2 Status. Read only.
0 Counting downward
1 Counting upward
Bit 13 T1STAT. GP timer 1 Status. Read only.
0 Counting downward
1 Counting upward
Bits 12–11 Reserved. Reads return zero; writes have no effect.
Bits 10–9 T2TOADC. Start ADC with timer 2 event.
00 No event starts ADC.
01 Setting of underflow interrupt flag starts ADC.
10 Setting of period interrupt flag starts ADC.
11 Setting of compare interrupt flag starts ADC.