Specifications

General-Purpose (GP) Timers
6-32
Bits 10–8 TPS2–TPS0. Input Clock Prescaler.
000 x/1 100 x/16
001 x/2 101 x/32
010 x/4 110 x/64
011 x/8 111 x/128
x = device (CPU) clock frequency
Bit 7 T2SWT1. In case of EVA, this bit is T2SWT1. (GP timer 2 start with GP timer 1.)
Start GP timer 2 with GP timer 1’s timer enable bit. This bit is reserved in
T1CON.
T4SWT3. In case of EVB, this bit is T4SWT3. (GP timer 4 start with GP timer 3.)
Start GP timer 4 with GP timer 3’s timer enable bit. This bit is reserved in
T3CON.
0 Use own TENABLE bit.
1 Use TENABLE bit of T1CON to enable and disable operation
ignoring own
TENABLE bit.
Bit 6 TENABLE. Timer enable.
0 Disable timer operation (the timer is put in hold and the prescaler
counter is reset).
1 Enable timer operations.
Bits 5–4 TCLKS1, TCLKS0. Clock Source Select.
5 4 Timer 1 Timer 2
0 0 Internal Internal
0 1 External External
1 0 Reserved Reserved
1 1 Reserved QEP Circuit
†
†
This option is valid only if SELT1PR = 0
Bits 3–2 TCLD1, TCLD0. Timer Compare Register Reload Condition.
00 When counter is 0.
01 When counter value is 0 or equals period register value.
10 Immediately
11 Reserved