Specifications

General-Purpose (GP) Timers
6-31 Event Manager (EV)
6.3.3 Timer Control Registers (TxCON and GPTCONA/B)
The addresses of the GP timer registers are given in Table 6–3 and Table 6–4
on page 6-11. The bit definition of the individual GP timer control registers,
TxCON, is shown in Figure 6–9. The bit definition of the overall GP timer con-
trol registers, GPTCONA and GPTCONB, are shown in Figure 6–10 (on
page 6-33) and Figure 6–11 (on page 6-34), respectively.
Individual GP Timer Control Register (TxCON; x = 1, 2, 3, or 4)
Figure 6–9. Timer Control Register (TxCON; x = 1, 2, 3, or 4) — Addresses 7404h (T1),
7408h (T2), 7504h (T3), and 7508h (T4)
15 14 13 12 11 10 9 8
Free
Soft Reserved TMODE1 TMODE0 TPS2 TPS1 TPS0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
T2SWT1/
T4SWT3
TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR
SELT1PR/
SELT3PR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–14 Free, Soft. Emulation control bits.
00 Stop immediately on emulation suspend.
01 Stop after current timer period is complete on emulation suspend.
10 Operation is not affected by emulation suspend.
11 Operation is not affected by emulation suspend.
Bit 13 Reserved. Reads return zero, writes have no effect.
Bits 12–11 TMODE1–TMODE0. Count Mode Selection.
00 Stop/Hold
01 Continuous-Up/-Down Count Mode
10 Continuous-Up Count Mode
11 Directional-Up/-Down Count Mode