Specifications
General-Purpose (GP) Timers
6-30
All GP timer PWM outputs are put in the high-impedance state when any of
the following events occurs:
- GPTCONA/B[6] is set to 0 by software
- PDPINTx is pulled low and is not masked
- Any reset event occurs
- TxCON[1] is set to 0 by software
Active/Inactive Time Calculation
For the continuous up-counting mode, the value in the compare register repre-
sents the elapsed time between the beginning of a period and the occurrence
of the first compare match, that is, the length of the inactive phase. This
elapsed time is equal to the period of the scaled input clock multiplied by the
value of TxCMPR. Therefore, the length of the active phase (the output pulse
width) is given by (TxPR) – (TxCMPR) + 1 cycle of the scaled input clock.
For the continuous up-/down-counting mode, the compare register can have
a different value while counting down from the value while counting up. The
length of the active phase, that is, the output pulse width, for up-/down-count-
ing modes is given by (TxPR) – (TxCMPR)
up
+ (TxPR) – (TxCMPR)
dn
cycles
of the scaled input clock, where (TxCMPR)
up
is the compare value on the way
up and (TxCMPR)
dn
is the compare value on the way down.
When the value in TxCMPR is 0, the GP timer compare output is active for the
whole period if the timer is in the up-counting mode. For the up-/down-counting
mode, the compare output is active at the beginning of the period if
(TxCMPR)
up
is 0. The output remains active until the end of the period if
(TxCMPR)
dn
is also 0.
The length of the active phase (the output pulse width) is 0 when the value of
TxCMPR is greater than that of TxPR for up-counting modes. For the up-/
down-counting mode, the first transition is lost when (TxCMPR)
up
is greater
than or equal to (TxPR). Similarly, the second transition is lost when
(TxCMPR)
dn
is greater than or equal to (TxPR). The GP timer compare output
is inactive for the entire period if both (TxCMPR)
up
and TxCMPR)
dn
are greater
than or equal to (TxPR) for the up-/down-counting mode.
Figure 6–7,
GP Timer Compare/PWM Output in Up-Counting Mode
(page 6-27) shows the compare operation of a GP timer in the up counting
mode. Figure 6–8,
GP Timer Compare/PWM Output in Up-/Down-Counting
Modes
(page 6-28) shows the compare operation of a GP timer in the up-/
down-counting mode.