Specifications

General-Purpose (GP) Timers
6-29 Event Manager (EV)
Output Logic
The output logic further conditions the output of the waveform generator to
form the ultimate PWM output that controls different kinds of power devices.
The PWM output can be specified active high, active low, forced low, and
forced high by proper configuration of the appropriate GPTCONA/B bits.
The polarity of the PWM output is the same as that of the output of the associat-
ed asymmetric/symmetric waveform generator when the PWM output is speci-
fied active high.
The polarity of the PWM output is the opposite of that of the output of the asso-
ciated asymmetric/symmetric waveform generator when the PWM output is
specified active low.
The PWM output is set to 1 (or 0) immediately after the corresponding bits in
GPTCONA/B are set, and the bit pattern specifies that the state of PWM output
is forced high (or low).
In summary, during a normal counting mode, transitions on the GP timer PWM
outputs happen according to Table 6–11 for the continuous up-counting mode
and according to Table 6–12 for the continuous up-/down-counting mode, as-
suming compare is enabled.
Setting active means setting high for active high and setting low for active low.
Setting inactive means the opposite.
The asymmetric/symmetric waveform generation, based on the timer counting
mode and the output logic, is also applicable to the compare units.
Table 6–11. GP Timer Compare Output in Continuous Up-Counting Modes
Time in a period State of Compare Output
Before compare match Inactive
On compare match Set active
On period match
Set inactive
Table 6–12. GP Timer Compare Output in Continuous Up-/Down-Counting Modes
Time in a period State of Compare Output
Before 1st compare match Inactive
On 1st compare match Set active
On 2nd compare match Set inactive
After 2nd compare match
Inactive