Specifications

General-Purpose (GP) Timers
6-28
- Toggles on the first compare match
- Remains unchanged until the second compare match
- Toggles on the second compare match
- Remains unchanged until the end of the period
- Resets to 0 at the end of the period if there is no second compare match,
and the new compare value for the following period is not 0
The output is set to 1 at the beginning of a period and remains 1 until the sec-
ond compare match if the compare value is 0 at the beginning of a period. After
the first transition, the output remains 1 until the end of the period if the
compare value is 0 for the second half of the period. When this happens, the
output does not reset to 0 if the new compare value for the following period is
still 0. This is done again to assure the generation of PWM pulses of 0% to
100% duty cycle without any glitches. The first transition does not happen if
the compare value is greater than or equal to that of the period register for the
first half of the period. However, the output still toggles when a compare match
happens in the second half of the period. This error in output transition, often
as a result of calculation error in the application routine, is corrected at the end
of the period because the output resets to 0, unless the new compare value
for the following period is 0. In this case, the output remains 1, which again puts
the output of the waveform generator in the correct state.
Note:
The output logic determines what the active state is for all output pins.
Figure 6–8. GP Timer Compare/PWM Output in Up-/Down-Counting Modes
Timer
(PWM)
period 1
Timer
(PWM)
period 2
Active
Inactive
Reloaded
comp value
greater
than period
Timer value
x
PWM/TxCMP
active low
x
PWM/TxCMP
active high
Compare matches
Compare
match