Specifications

General-Purpose (GP) Timers
6-27 Event Manager (EV)
- toggles on compare match
- remains unchanged until the end of the period
- resets to 0 at the end of a period on period match, if the new compare value
for the following period is not 0
The output is 1 for the whole period, if the compare value is 0 at the beginning
of a period. The output does not reset to 0 if the new compare value for the
following period is 0. This is important because it allows the generation of PWM
pulses of 0% to 100% duty cycle without glitches. The output is 0 for the whole
period if the compare value is greater than the value in the period register. The
output is 1 for one cycle of the scaled clock input if the compare value is the
same as that of the period register.
One characteristic of asymmetric PWM waveforms is that a change in the val-
ue of the compare register only affects one side of the PWM pulse.
Figure 6–7. GP Timer Compare/PWM Output in Up-Counting Mode
Timer
(PWM)
period 1
Timer
(PWM)
period 2
Compare
match
Active
InactiveInactive
Active
New comp
value greater
than period
Timer value
TxPWM/TxCMP
active low
TxPWM/TxCMP
active high
Compare matches
Symmetric Waveform Generation
A symmetric waveform (Figure 6–8) is generated when the GP timer is in con-
tinuous up-/down-counting modes. When the GP timer is in this mode, the
state of the output of the waveform generator is determined by the following:
- 0 before the counting operation starts
- Remains unchanged until first compare match