Specifications

General-Purpose (GP) Timers
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6.3.2 GP Timer Compare Operation
Each GP timer has an associated compare register TxCMPR and a PWM out-
put pin TxPWM. The value of a GP timer counter is constantly compared to that
of its associated compare register. A compare match occurs when the value
of the timer counter is the same as that of the compare register. Compare op-
eration is enabled by setting TxCON[1] to 1. If it is enabled, the following hap-
pens on a compare match:
- The compare interrupt flag of the timer is set one clock cycle after the
match.
- A transition occurs on the associated PWM output according to the bit con-
figuration in GPTCONA/B, one device clock cycle after the match.
- If the compare interrupt flag has been selected by the appropriate
GPTCONA/B bits to start ADC, an ADC start signal is generated at the
same time the compare interrupt flag is set.
A peripheral interrupt request is generated by the compare interrupt flag if it
is unmasked.
PWM Transition
The transition on the PWM output is controlled by an asymmetric and symmet-
ric waveform generator and the associated output logic, and depends on the
following:
- Bit definition in GPTCONA/B
- Counting mode the timer is in
- Counting direction when the counting mode is continuous-up/-down mode
Asymmetric/Symmetric Waveform Generator
The asymmetric/symmetric waveform generator generates an asymmetric or
symmetric PWM waveform based on the counting mode the GP timer is in.
Asymmetric Waveform Generation
An asymmetric waveform (Figure 6–7) is generated when the GP timer is in
continuous up-counting mode. When the GP timer is in this mode, the output
of the waveform generator changes according to the following sequence:
- 0 before the counting operation starts
- remains unchanged until the compare match happens