Specifications

General-Purpose (GP) Timers
6-23 Event Manager (EV)
Figure 6–4. GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2)
TxPR=4–1=3 TxPR=3–1=2
3
2
1
0
3
2
1
00
2
1
0
Timer value
TxCON[6]
Timer clock
As shown in Figure 6–4, GP Timer Continuous Up-Counting Mode (TxPR =
3 or 2) , no clock cycle is missed from the time the counter reaches the period
register value to the time it starts another counting cycle.
Directional Up-/Down-Counting Mode
The GP timer in directional up-/down-counting mode counts up or down ac-
cording to the scaled clock and TDIRA/B inputs. The GP timer starts counting
up until its value reaches that of the period register (or FFFFh if the initial count
is greater than the period) when the TDIRA/B pin is held high. When the timer
value equals that of its period register (or FFFFh) the timer resets to zero and
continues counting up to the period again. When TDIRA/B is held low, the GP
timer counts down until its value becomes 0. When the value of the timer has
counted down to 0, the timer reloads its counter with the value in the period
register and starts counting down again.
The initial value of the timer can be any value between 0000h to FFFFh. When
the initial value of the timer counter is greater than that of the period register,
the timer counts up to FFFFh before resetting itself to 0 and counting up to the
period. If TDIRA/B is low when the timer starts with a value greater than the
period register, it counts down to the value of the period register and continues
counting down to 0, at which point the timer counter gets reloaded with the val-
ue from the period register as normal.
The period, underflow, and overflow interrupt flags, interrupts, and associated
actions are generated on respective events in the same manner as they are
generated in the continuous up-counting mode.
The latency from a change of TDIRA/B to a change of counting direction is one
clock cycle after the end of the current count (that is, after the end of the current
prescale counter period).