Specifications

General-Purpose (GP) Timers
6-22
One clock cycle after the GP timer becomes 0, the underflow interrupt flag of
the timer is set. A peripheral interrupt request is generated by the flag if it is
unmasked. An ADC start is sent to the ADC module at the same time if the un-
derflow interrupt flag of this timer has been selected by appropriate bits in
GPTCONA/B to start ADC.
The overflow interrupt flag is set one clock cycle after the value in TxCNT
matches FFFFh. A peripheral interrupt request is generated by the flag if it is
unmasked.
The duration of the timer period is (TxPR) + 1 cycles of the scaled clock input
except for the first period. The duration of the first period is the same if the timer
counter is 0 when counting starts.
The initial value of the GP timer can be any value between 0h and FFFFh inclu-
sive. When the initial value is greater than the value in the period register, the
timer counts up to FFFFh, resets to 0, and continues the operation as if the
initial value was 0. When the initial value in the timer counter is the same as
that of the period register, the timer sets the period interrupt flag, resets to 0,
sets the underflow interrupt flag, and then continues the operation again as if
the initial value was 0. If the initial value of the timer is between 0 and the con-
tents of the period register, the timer counts up to the period value and continue
to finish the period as if the initial counter value was the same as that of the
period register.
The counting direction indication bit in GPTCONA/B is 1 for the timer in this
mode. Either the external or internal device clock can be selected as the input
clock to the timer. TDIRA/B input is ignored by the GP timer in this counting
mode.
The continuous up-counting mode of the GP timer is particularly useful for the
generation of edge-triggered or asynchronous PWM waveforms and sampling
periods in many motor and motion control systems.
Figure 6–4 shows the continuous up-counting mode of the GP timer.