Specifications

General-Purpose (GP) Timers
6-21 Event Manager (EV)
a period event happens when the value of the timer counter is the same as that
of the period register. The overflow, underflow, and period interrupt flags of the
timer are set one clock cycle after the occurrence of each individual event.
Note that the definition of overflow and underflow is different from their conven-
tional definitions.
6.3.1 GP Timer Counting Operation
Each GP timer has four possible modes of operation:
- Stop/Hold mode
- Continuous Up-Counting mode
- Directional Up-/Down-Counting mode
- Continuous Up-/Down-Counting mode
The bit pattern in the corresponding timer control register TxCON determines
the counting mode of a GP timer. The timer enabling bit, TxCON[6], enables
or disables the counting operation of a timer. When the timer is disabled, the
counting operation of the timer stops and the prescaler of the timer is reset
to x/1. When the timer is enabled, the timer starts counting according to the
counting mode specified by other bits of TxCON.
Stop/Hold Mode
In this mode the GP timer stops and holds at its current state. The timer count-
er, the compare output, and the prescale counter all remain unchanged in this
mode.
Continuous Up-Counting Mode
The GP timer in this mode counts up according to the scaled input clock until
the value of the timer counter matches that of the period register. On the next
rising edge of the input clock after the match, the GP timer resets to 0 and starts
counting up again.
The period interrupt flag of the timer is set one clock cycle after the match be-
tween the timer counter and period register. A peripheral interrupt request is
generated if the flag is not masked. An ADC start is sent to the ADC module
at the same time the flag is set, if the period interrupt of this timer has been
selected by the appropriate bits in GPTCONA/B to start the ADC.