Specifications

General-Purpose (GP) Timers
6-20
This allows the desired synchronization between GP timer events. Since each
GP timer starts the counting operation from its current value in the counter reg-
ister, one GP timer can be programmed to start with a known delay after the
other GP timer.
Starting the A/D Converter with a Timer Event
The bits in GPTCONA/B can specify that an ADC start signal be generated on
a GP timer event such as underflow, compare match, or period match. This
feature provides synchronization between the GP timer event and the ADC
start without any CPU intervention.
GP Timer in Emulation Suspend
The GP timer control register bits also define the operation of the GP timers
during emulation suspend. These bits can be set to allow the operation of GP
timers to continue when an emulation interrupt occurs making in-circuit emula-
tion possible. They can also be set to specify that the operation of GP timers
stops immediately, or after completion of the current counting period, when
emulation interrupt occurs.
Emulation suspend occurs when the device clock is stopped by the emulator,
for example, when the emulator encounters a break point.
GP Timer Interrupts
There are sixteen interrupt flags in EVAIFRA, EVAIFRB, EVBIFRA, and EV-
BIFRB registers for the GP timers. Each of the four GP timers can generate
four interrupts upon the following events:
- Overflow: TxOFINT (x = 1, 2, 3, or 4)
- Underflow: TxUFINT (x = 1, 2, 3, or 4)
- Compare match: TxCINT (x = 1, 2, 3, or 4)
- Period match: TxPINT (x = 1, 2, 3, or 4)
A timer compare event (match) happens when the content of a GP timer count-
er is the same as that of the compare register. The corresponding compare
interrupt flag is set one clock cycle after the match if the compare operation
is enabled.
An overflow event occurs when the value of the timer counter reaches FFFFh.
An underflow event occurs when the timer counter reaches 0000h. Similarly,