Specifications

General-Purpose (GP) Timers
6-19 Event Manager (EV)
GP timer 4 (EVB) can be used with the QEP circuits, in directional up-/down-
counting mode. In this case, the QEP circuits provide both the clock and direc-
tion inputs to the timer.
A wide range of prescale factors are provided for the clock input to each GP
timer.
QEP-Based Clock Input
The quadrature encoder pulse (QEP) circuit, when selected, can generate the
input clock and counting direction for GP timer 2/4 in the directional up-/down-
counting mode. This input clock cannot be scaled by GP timer prescaler cir-
cuits (that is, the prescaler of the selected GP timer is always 1 if the QEP cir-
cuit is selected as the clock source). Furthermore, the frequency of the clock
generated by the QEP circuits is four times that of the frequency of each QEP
input channel because both the rising and falling edges of both QEP input
channels are counted by the selected timer. The frequency of the QEP input
must be less than or equal to one-fourth of that of the device clock.
GP Timer Synchronization
GP timer 2 can be synchronized with GP timer 1 (for EVA) and GP timer 4 can
be synchronized with GP timer 3 (for EVB) by proper configuration of T2CON
and T4CON, respectively, in the following ways:
- EVA:
Set the T2SWT1 bit in T2CON to start GP timer 2 counting with the TEN-
ABLE bit in T1CON (thus, both timer counters start simultaneously).
- EVA:
Initialize the timer counters in GP timers 1 and 2 with different values be-
fore starting synchronized operation.
- EVA:
Specify that GP timer 2 uses the period register of GP timer 1 as its period
register (ignoring its own period register) by setting SELT1PR in T2CON.
- EVB:
Set the T4SWT3 bit in T4CON to start GP timer 4 counting with the TEN-
ABLE bit in T3CON (thus, both timer counters start simultaneously).
- EVB:
Initialize the timer counters in GP timers 3 and 4 with different values be-
fore starting synchronized operation.
- EVB:
Specify that GP timer 4 uses the period register of GP timer 3 as its period
register (ignoring its own period register) by setting SELT3PR in T4CON.