Specifications

General-Purpose (GP) Timers
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a period in order to change the timer period and the width of the PWM pulse
for the period that follows. On-the-fly change of the timer period value, in the
case of PWM generation, means on-the-fly change of PWM carrier frequency.
Caution :
The period register of a GP timer should be initialized before its counter
is initialized to a non-zero value. Otherwise, the value of the period
register will remain unchanged until the next underflow.
Note that a compare register is transparent (the newly loaded value goes di-
rectly into the active register) when the associated compare operation is dis-
abled. This applies to all Event Manager compare registers.
GP Timer Compare Output
The compare output of a GP timer can be specified active high, active low,
forced high, or forced low, depending on how the GPTCONA/B bits are config-
ured. It goes from low to high (high to low) on the first compare match when
it is active high (low). It then goes from high to low (low to high) on the second
compare match if the GP timer is in an up-/down-counting mode, or on period
match if the GP timer is in up-counting mode. The timer compare output be-
comes high (low) right away when it is specified to be forced high (low).
Timer Counting Direction
The counting directions of the GP timers are reflected by their respective bits
in GPTCONA/B during all timer operations as follows:
- 1 represents the up-counting direction.
- 0 represents the down-counting direction.
The input pin TDIRA/B determines the direction of counting when a GP timer
is in directional up-/down-counting mode. When TDIRA/B is high, upward
counting is specified; when TDIRA/B is low, downward counting is specified.
Timer Clock
The source of the GP timer clock can be the internal device clock or the exter-
nal clock input, TCLKINA/B. The frequency of the external clock must be less
than or equal to one-fourth of that of the device clock. GP timer 2 (EVA) and