Specifications

General-Purpose (GP) Timers

6-17

Event Manager (EV)

GP Timer Compare Registers

The compare register associated with a GP timer stores the value to be

constantly compared with the counter of the GP timer. When a match happens,

the following events occur:

- A transition occurs on the associated compare output according to the bit

pattern in GPTCONA/B.

- The corresponding interrupt flag is set.

- A peripheral interrupt request is generated if the interrupt is unmasked.

The compare operation of a GP timer can be enabled or disabled by the ap-

propriate bit in TxCON.

The compare operation and outputs can be enabled in any of the timer modes,

including QEP mode.

GP Timer Period Register

The value in the period register of a GP timer determines the period of the tim-

er. A GP timer resets to 0, or starts counting downward when a match occurs

between the period register and the timer counter, depending on which count-

ing mode the timer is in.

Double Buffering of GP Timer Compare and Period Registers

The compare and period registers, TxCMPR and TxPR, of a GP timer are

shadowed. A new value can be written to any of these registers at any time

during a period. However, the new value is written to the associated shadow

into the working (active) register only when a certain timer event specified by

TxCON occurs. For the period register, the working register is reloaded with

the value in its shadow register only when the value of the counter register

TxCNT is 0. The condition on which a compare register is reloaded can be one

of the following:

- Immediately after the shadow register is written

- On underflow; that is, when the GP timer counter value is 0

- On underflow or period match; that is, when the counter value is 0 or when

the counter value equals the value of the period register

The double buffering feature of the period and compare registers allows the

application code to update the period and compare registers at any time during