Specifications

General-Purpose (GP) Timers
6-16
- Direction input, TDIRA/B, for use by the GP timers in directional up-/down-
counting mode.
- Reset signal, RESET.
When a timer is used with the QEP circuit, the QEP circuit generates both the
timer’s clock and the counting direction.
GP Timer Outputs
The outputs of the timers are:
- GP timer compare outputs TxCMP, x = 1, 2, 3, 4
- ADC start-of-conversion signal to ADC module
- Underflow, overflow, compare match, and period match signals to its own
compare logic and to the compare units
- Counting direction indication bits
Individual GP Timer Control Register (TxCON)
The operational mode of a timer is controlled by its individual control register
TxCON. Bits in the TxCON register determine:
- Which of the four counting modes the timer is in
- Whether an internal or external clock is to be used by the GP Timer
- Which of the eight input clock prescale factors (ranging from 1 to 1/128)
is used
- On which condition the timer compare register is reloaded
- Whether the timer is enabled or disabled
- Whether the timer compare operation is enabled or disabled
- Which period register is used by timer 2, its own, or timer 1’s period register
(EVA)
Which period register is used by timer 4, its own, or timer 3’s period register
(EVB)
Overall GP Timer Control Register (GPTCONA/B)
The control register GPTCONA/B specifies the action to be taken by the timers
on different timer events and indicates their counting directions.