Specifications

General-Purpose (GP) Timers
6-15 Event Manager (EV)
Figure 6–3. General-Purpose Timer Block Diagram (x = 2 or 4)
[when x = 2: y = 1 and n = 2; when x = 4: y = 3 and n = 4]
TxPR
period register
(shadowed)
TyPR period
register (shad-
owed)
TxCMPR
compare
register
(shadowed)
Compare
logic
MUX
Symm/asym
waveform
generator
GPTCONA/B
GP timer
control
register
Output
logic
TxCNT GP
timer counter
Control
logic
TxCON
GPTx control
register
Interrupt flags
TxPWM
ADC start of
conversion
TCLKINA/B
TDIRA/B
Internal
CPU
clock
TnCON[0]
GP Timer Inputs
The inputs to the GP timers are:
- The internal device (CPU) clock.
- An external clock, TCLKINA/B, that has a maximum frequency of one-
fourth that of the device clock.