Specifications

Event Manager (EV) Functional Blocks
6-10
- CPU response . On receipt of INT1, 2, 3, or 4 interrupt request, the respec-
tive bit in the CPU interrupt flag register (IFR) will be set. If the correspon-
ding interrupt mask register (IMR) bit is set and INTM bit is cleared, then
the CPU recognizes the interrupt and issues an acknowledgement to the
PIE. Following this, the CPU finishes executing the current instruction and
branches to the interrupt vector corresponding to INT1, 2, 3, or 4. At this
time, the respective IFR bit will be cleared and the INTM bit will be set dis-
abling further interrupt recognition. The interrupt vector contains a branch
instruction for the interrupt service routine. From here, the interrupt re-
sponse is controlled by the software.
- PIE response . The PIE logic uses the acknowledge signal from the core
to clear the PIRQ bit that issued the CPU interrupt. Along with this, the PIE
updates its PIVR register with the interrupt vector, unique to the peripheral
interrupt, that was just acknowledged. After this, the PIE hardware works
in parallel to the current interrupt software to generate aCPU interrupt and
other pending interrupts, if any.
- Interrupt software . The interrupt software has two levels of response.
J Level 1 (GISR). In the first level the software should do any context
save and read the PIVR register from PIE module to decide which in-
terrupt group caused the interrupt.Since the PIVR value is unique, it
can be used to branch to the interrupt service routine specific to this
interrupt condition.
J Level 2 (SISR). This level is optional and could reside as a part of lev-
el 1. However, at this stage the interrupt software has explicit respon-
sibility to avoid improper interrupt response. After executing the inter-
rupt specific code, the routine should clear the interrupt flag in the
EVxIFRA EVxIFRB, or EVxIFRC that caused the serviced interrupt.
Code will return after enabling the CPU’s global interrupt bit INTM
(clear INTM bit).