Specifications
Event Manager (EV) Functional Blocks
6-9
Event Manager (EV)
6.1.4 EV Registers
The Event Manager registers occupy two 64-word (16-bit) frames of address
space. The Event Manager module decodes the lower 6-bits of the address;
while the upper 10 bits of the address are decoded by the peripheral address
decode logic, which provides a module select to the Event Manager when the
peripheral address bus carries an address within the range designated for the
EV on that device.
On the ’240x devices (as with the ’C240 device), EVA registers are located in
the range 7400h to 7431h. EVB registers are located in the range of 7500h to
7531h.
The undefined registers and undefined bits of the EV registers all return zero
when read by user software. Writes have no effect. See Section 6.2, on
page 6-11.
6.1.5 EV Interrupts
The event manager interrupts are arranged into three groups. Each group is
assigned one CPU interrupt (INT2, 3 or 4). Since each group has multiple inter-
rupt sources, the CPU interrupt requests are processed by the Peripheral In-
terrupt Expansion module. The ’240x interrupt requests have the following
stages of response:
-
Interrupt source
. If peripheral interrupt conditions occur, the respective
flag bits in registers EVxIFRA, EVxIFRB, or EVxIFRC (x = A or B) are set.
Once set, these flags remain set until explicity cleared by the software. It
is mandatory to clear these flags in the software or future interrupts will not
be recognized.
-
Interrupt enable
. The event manager interrupts can be individually enable-
d or disabled by interrupt mask registers EVxIMRA, EVxIMRB, and
EVxIMRC (x = A or B). Each bit is set to 1 to enable/unmask the interrupt
or cleared to 0 to disable/mask the interrupt.
-
PIE request
. If both interrupt flag bits and interrupt mask bits are set, then
the peripheral issues a peripheral interrupt request to the PIE module. The
PIE module can receive more than one interrupt from the peripheral. The
PIE logic records all the interrupt requests and generates the respective
CPU interrupt (INT1, 2, 3, or 4) based on the preassigned priority of the
received interrupts. See Table 2–2,
’240x Interrupt Source Priority and
Vectors
, on page 2-8 for priority and vector values.