Specifications

Event Manager (EV) Functional Blocks
6-5 Event Manager (EV)
6.1.1 Differences Between ’C240 EV and ’240x EV
- The single-up count and single-up/down count modes have been re-
moved from the remaining GP timers.
Software change: The four timer
modes are now decoded with TMODE1–0. This decoding is different from
the ’C240 EV. TMODE2 is now a reserved bit.
- There is no 32-bit timer mode.
- The GP Timers do not stay at the period register value, FFFFh or 0000h
when operating in directional-up/down count mode (including QEP mode).
They now reverse direction when one of these end points is reached.
- A capture 3 event is now able to start the ADC.
- The capture units of a particular EV can now use any timer associated with
that EV as a time base.
- The capture interrupt flag gets set when a capture event occurs only if
there are one or more capture events stored in the FIFO already.
- The Capture FIFO status bits are now RW. Bits 5–0 of CAPFIFO are now
unnecessary and are reserved.
- Both locations in the capture FIFO can be read individually, not just the top
location.
- The QEP logic can only clock GP timer 2 for EVA and GP timer 4 for EVB.
- The three simple compare units have been removed.
- The compare mode of the (full) compare units has been removed. They
now only operate in PWM mode.
- The dead band counters have been reduced from 8 bits to 4 bits. The dead
band prescaler has been increased from 3 bits to 5 bits, adding two more
prescale values: x/16 and x/32.
Software change: There are now three
DBTPSx bits. DBTPS0 moves to bit 2 of DBTCON, DBTPS1 moves to bit 3
and bit 4 becomes DBTPS2.
- Any register bits associated with the removed functions are now reserved
(not implemented).
- Most interrupt control logic has been removed from each peripheral. Each
peripheral now simply has one interrupt request signal and associated en-
able for each interrupt flag. The peripheral interrupt vector table (contain-
ing the peripheral interrupt vectors) is now located in the peripheral inter-
rupt expansion (PIE) controller.