Specifications

Data and Direction Control Registers
5-15 Digital Input/Output (I/O)
Figure 5–10. Port F Data and Direction Control Register (PFDATDIR)
15 14 13 12 11 10 9 8
Reserved F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
Reserved IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bit 15 Reserved
Bits 14–8 FnDIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bit 7 Reserved
Bits 6–0 IOPFn
If FnDIR = 0, then:
0 Corresponding I/O pin is read as a low .
1 Corresponding I/O pin is read as a high .
If FnDIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .
Table 5–10. PFDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)
I/O Port Data Bit Pin Name
IOPF0 CAP5/QEP4/IOPF0
†
IOPF1 CAP6/IOPF1
†
IOPF2 T3PWM/T3CMP/IOPF2
†
IOPF3 T4PWM/T4CMP/IOPF3
†
IOPF4 TDIR2/IOPF4
†
IOPF5 TCLKIN2/IOPF5
†
IOPF6 IOPF6
†
Reserved Reserved
†
These pins are not available in ’2402 devices.