Specifications

Data and Direction Control Registers
5-14
Figure 5–9. Port E Data and Direction Control Register (PEDATDIR)
15 14 13 12 11 10 9 8
E7DIR
E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
76543210
IOPE7
IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–8 EnDIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bits 7–0 IOPEn
If EnDIR = 0, then:
0 Corresponding I/O pin is read as a
low .
1 Corresponding I/O pin is read as a high .
If EnDIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .
Table 5–9. PEDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)
I/O Port Data Bit Pin Name
IOPE0 CLKOUT/IOPE0
IOPE1 PWM7/IOPE1
†
IOPE2 PWM8/IOPE2
†
IOPE3 PWM9/IOPE3
†
IOPE4 PWM10/IOPE4
†
IOPE5 PWM11/IOPE5
†
IOPE6 PWM12/IOPE6
†
IOPE7 CAP4/QEP3/IOPE7
†
†
These pins are not available in ’2402 devices.