Specifications

Data and Direction Control Registers
5-13 Digital Input/Output (I/O)
Figure 5–8. Port D Data and Direction Control Register (PDDATDIR)
15–9 8
Reserved D0DIR
RW-0
7–1 0
Reserved IOPD0
RW-0
Note: R = Read access, W = Write access, -0 = value after reset
Bits 15–9 Reserved
Bit 8 D0DIR
0 Configure corresponding pin as an input.
1 Configure corresponding pin as an output.
Bits 7–1 Reserved
Bit 0 IOPD0
If D0DIR = 0, then:
0 Corresponding I/O pin is read as a low .
1 Corresponding I/O pin is read as a high .
If D0DIR = 1, then:
0 Set corresponding I/O pin low .
1 Set corresponding I/O pin high .
Table 5–8. PDDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)
I/O Port Data Bit Pin Name
IOPD0 XINT2/ADCSOC/IOPD0
IOPD1 Reserved
IOPD2 Reserved
IOPD3 Reserved
IOPD4 Reserved
IOPD5 Reserved
IOPD6 Reserved
IOPD7
Reserved